1. Field of the Invention
The present invention relates to computer interface circuits, and in particular, to computer interface circuits operating in a control environment and providing asynchronous interrupt service to multiple peripheral devices.
2. Description of the Related Art
The types of computer interface circuit designs available, as well as their applications, are virtually unlimited in number. As computers have become more prevalent and their applications more varied, more interface circuit designs have become necessary for providing the appropriate interface between the computers and their operating environments.
A common type of computer interface circuit is designed for operating in a control environment in which interrupt service must be provided for multiple peripheral devices. For example, referring to FIG. 1, a typical design for such an interface circuit 10 includes: read 12 and write 14 buffers; a decoder 16; a parallel input-output controller ("PIO") 18; a dual universal asynchronous receiver-transmitter ("UART") 20; a microprocessor (".mu.P") 22; a read-only memory ("ROM") 24; and a random-access memory ("RAM") 26, substantially as shown.
Incoming data from the data bus of a host computer (not shown) is captured and held by the write buffer 14. This data is then transferred via the PIO 18, under control of the .mu.P 22, to the RAM 26 for temporary storage before subsequently being transferred to a peripheral device (not shown) via the dual UART 20. Data coming from a peripheral device via the dual UART 20 is stored in the RAM 26, and then, under control of the .mu.P 22, is transferred to the data bus of the host computer via the PIO 18 and read buffer 12. The read 12 and write 14 buffers are appropriately enabled or disabled by the decoder 16, which is controlled by the host computer via its address bus.
A problem with this conventional interface circuit design involves the need for and use of the read 12 and write 14 buffers, the PIO 18 and RAM 26. This configuration produces a data bottleneck which excessively "loads down" the host computer, i.e. with respect to the host computer's involvement time with the operation of the interface circuit 10. Particularly where the interface circuit 10 is used for servicing interrupts for the peripheral devices, this configuration results in the host computer standing by in a wait, or idle, mode while the .mu.P 22 transfers data for servicing the interrupt. Virtually all data communication between the host computer and the interface circuit 10 (e.g. the .mu.P 22) uses the PIO 18. Thus, while the .mu.P 22 is retrieving data from the write buffer 14 via the PIO 18 and storing it in the RAM 26, or retrieving data from the RAM 26 for transfer to the read buffer 12 via the PIO 18, the host computer must wait.
Therefore, it would be desirable to have a computer interface circuit for operating in a control environment for servicing interrupts for peripheral devices, wherein such interface functions can be performed asynchronously with respect to the operation of the host computer, and with minimal interaction time required on the part of the host computer.